View HD64F3048TFI16_6658210.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

h8/300h series microcontrollers
notice when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications.
i contents welcome .... .....................................................................................................1 cpu ........... .....................................................................................................5 addressing . .....................................................................................................7 addressing modes ................................................................................................................. 7 instruction set ..................................................................................................9 arithmetic instructions .......................................................................................................... 10 bit processing........................................................................................................................ 11 block move instruction ......................................................................................................... 12 software interrupt.................................................................................................................. 12 cpu states / low power modes .......................................................................13 low power modes ................................................................................................................. 13 sleep mode............................................................................................................................ 13 software standby mode......................................................................................................... 13 hardware standby mode........................................................................................................ 14 extra power down support - h8 / 3048 ................................................................................. 14 clock gearing........................................................................................................................ 15 exceptions and interrupts .................................................................................17 trap exceptions..................................................................................................................... 18 interrupt controller................................................................................................................ 18 h8 / 300 compatible mode.................................................................................................... 18 h8 / 300h advanced mode.................................................................................................... 18 external interrupts ................................................................................................................. 18 interrupt vectors.................................................................................................................... 18 interrupt response time........................................................................................................ 19 on-chip memory..............................................................................................21 flash memory (f-ztat) .................................................................................23 technology............................................................................................................................ 24 bus state controller (bsc) ..............................................................................25 dram and psram interface ................................................................................................ 26 chip select generation .......................................................................................................... 27
ii direct memory access controller (dmac ) .................................................... . 29 short address mod e ............................................................................................................. . 3 0 full address mode ................................................................................................................ . 3 0 dmac interrupt s .................................................................................................................. . 3 0 dmac mode s ...................................................................................................................... . 3 0 integrated timer unit (itu ) ........................................................................... . 33 output compare function s ................................................................................................... . 35 input capture function s ........................................................................................................ . 35 timer synchronisatio n .......................................................................................................... . 3 5 pwm operating mode s ........................................................................................................ . 36 standard pwm mod e ........................................................................................................... . 3 6 ac motor control output s ................................................................................................... . 37 complementary 6-phase pw m ............................................................................................. . 37 reset synchronised pw m ..................................................................................................... . 38 phase counting mod e ........................................................................................................... . 3 8 itu interrupt s ....................................................................................................................... . 3 9 timing pattern controller (tpc ) .................................................................... . 41 stepper motor control with the tpc..................................................................................... . 41 watchdog timer (wdt ) ................................................................................. . 45 serial communications interface (sci ) ........................................................... . 47 analogue to digital converter (adc ) ............................................................. . 49 digital to analogue converter (dac ) ........................................................................ . 50 h8/300h summar y ......................................................................................... . 51 h8/3001 serie s ...................................................................................................................... . 5 5 h8/3002 serie s ...................................................................................................................... . 5 6 h8/3003 serie s ...................................................................................................................... . 5 7 h8/3004 and h8/3005 serie s ................................................................................................. . 58 h8/3032 serie s ...................................................................................................................... . 5 9 h8/3042 serie s ...................................................................................................................... . 6 0 h8/3048 serie s ...................................................................................................................... . 6 1 package s ............................................................................................................................... . 6 2 ordering informatio n ...................................................................................... . 63
1 welcome to hitachi's 16-bit microcontroller family h8/300h. h8/300h has enjoyed tremendous success since its introduction in 1993 as a successor to hitachi's equally successful h8/500 family. dataquest has found hitachi's 16-bit microcontrollers to be the most successful world-wide as well as in europe. siemens 11% sgs 13% intel 12% motorola 21% hitachi 23% others 13% nec 7% european 16-bit m m c market shares 1995 source:dataquest at hitachi europe we think that this success was driven by our strong commitment to be a leading force in the microcontroller marketplace and our belief that we must listen to our customer's requirements and then meet these. as h8/300h is the result of combining many years of experience of hitachi with the experience of our customers, h8/300h is an excellent example where this policy has worked for our customers and hitachi. the european electronics industry demands full service and support. at hitachi, we responded by setting up a european engineering and tool design subsidiary 12 years ago: hitachi microsystems europe (hmse) based in maidenhead (uk). hmse provides our customers with locally designed and supported tools ranging from low cost evaluation boards to fully featured real time emulators based on ibm-compatible pc's at a very competitive price. software ranges from assembler, an ansi c-compiler via a c-level debugger to hios, hitachi's real time operating system. to speed development hmse supplies makeapp, a tool that sets up peripherals and creates driver routines on the click of a mouse. hmse also offers support and engineering resources for customers wishing to use hitachi's asic capabilities. this also applies to our m cbic program, enabling our customers to select one of hitachi's cpu cores and combine it with peripherals from our library and adding customer specified logic via vhdl or verilog.
2 hitachi also provides two technical help lines with 24 hour response, based in maidenhead and munich, as well as local language application support in italy, france and scandinavia. all of this backed by strong support from third party tool manufacturers, like hewlett packard, pentica and lauterbach to name just a few. h8/300h is part of hitachi's software compatible h8 product range, which covers a performance range from 400ns to 50ns cycle time, whilst increasing word length from 8 to 16 bit and memory space from 64kb to 16mb. this product range offers an industry leading mix of memory options (including flash), peripherals and performance/power consumption, all of this being software compatible for protection of our customers software investment. hitachi produces and ships over 12 million h8 microcontrollers every month, in a vast range of advanced packaging and temperature options. h8/300h 90 h8/300l 91 92 93 94 95 96 97 h8/300 h8s faster more memory more integration 16bit, 16 mb address higher performance or less power consumption low power single chip h8/300h has the performance (up to 10 native mips), the peripherals (very powerful timers, 10- bit adc, serial communications, etc.) and the memory options (including h8/3048f with 128kb flash) to make it an industry standard in telecommunications and very successful in industrial (e.g. motor control) and emerging consumer applications like new electronic video cameras, set top boxes and advanced car radios. since its introduction h8/300h has been selected for hundreds of designs in europe alone.
3 now available! h8/3035 with 256k rom/otp and 4k ram h8/3003 rom-less 512 byte ram 112 pin qfp rich peripherals reduced pin count h8/3002 rom-less 512 byte ram 100 pin qfp rich peripherals reduced pin count reduced peripherals h8/3001 rom-less 512 byte ram 80 pin qfp reduced peripherals h8/3042 32k..64k rom 2k ram 100 pin qfp rich peripherals reduced pin count slightly reduced peripherals h8/3035 16k..256k rom 512byte..4k ram 80 pin qfp reduced peripherals rom-less reduced peripherals h8/3032 pin compatible h8/3004+ 3005 rom-less 2k..4k ram 80 pin qfp reduced peripherals h8/3048 32k..128k rom 2k..4k ram 100 pin qfp enhanced peripherals future 256k rom faster clock further enhanced peripherals
4
5 cpu the h8/300h cpu core has been designed as a 16/32 bit general purpose register machine. this architecture makes execution of software written in c very efficient and results in dense code in order to reduce the amount of memory needed. hence, h8/300h lowers total system cost. the h8/300h cpu is a general purpose register machine as shown below. the cpu comprises eight 32-bit registers, each being further dividable into 16 and 8-bit registers. being general purpose there is no restriction placed on how each register is used, thus they can be used for pointer or data operations. the architecture also allows any of the data addressing modes to be used in conjunction with any register. er0 r0l r0h e0 15 0 7 0 0 7 general registers (ern) er1 r1l r1h e1 er2 r2l r2h e2 er3 r3l r3h e3 er4 r4l r4h e4 er5 r5l r5h e5 er6 r6l r6h e6 er7 r7l r7h e7 (sp) pc 23 control registers (cr) 0 ccr 0 c 1 v 2 z 3 n 4 u 5 h 6 ui 7 i this rich set of general purpose registers provides the compiler writer with ample opportunities to optimise the code generated by the compiler. local variables can be optimised into registers wherever possible, thus reducing the number of bytes of code needed to manipulate them. also, because each register can be used as an accumulator, index register or address pointer, the address arithmetic which must be performed by the compiler can be done very effectively. register er7 is used as a stack pointer, so all accesses to stack based data can be performed very fast.
6 these features significantly reduce the amount of code and time that is required to execute lines of c source code when compared to traditional architectures, which have limited numbers of fixed function accumulators and index registers. the 32-bit register set also proves to be very useful in addressing large areas of memory, as a 24-bit pointer (this size pointer allows access to anywhere in the 16mbytes address space) can be stored and manipulated in one register. in addition to the general purpose registers there are two control registers, a condition code register (ccr) and a program counter (pc). the ccr is an 8-bit wide register which contains all the cpu flags such as overflow, zero and carry as well as the interrupt flags. the carry flag also doubles as a bit accumulator when the bit manipulation operations are used. the h8/300h cpu offers a h8/300 compatible mode which allows straightforward reuse of existing h8/300 software. this mode is available in h8/3032, h8/3042 and m cbic products.
7 addressing to support large memory systems the linear address space of the h8/300h cpu core allows direct access to every address in the whole 16mbyte address space via 24-bit address pointers. the linear address space means there is no need to set up page registers and there are also no limitations on the size of code modules or data arrays and structures. addressing modes another way a cpu architecture can support the efficiency of the compiler is by providing a full set of powerful and flexible addressing modes. a cpu which only provides rudimentary addressing modes makes a compiler inefficient in the access of variables, thereby increasing both code size and execution time. to ensure that the compiler is as efficient as possible the h8/300h cpu provides eight addressing modes as shown in the figure below. register direct rn register indirect @ e rn register indirect with displacement @ (d: 16, e rn) @ (d: 24, e rn) register indirect with post-increment/ @ e rn + @ - e rn register indirect with pre-decrement absolute address @ aa : 8 @ aa : 16 @ aa : 24 immediate # xx : 8 # xx : 16 # xx : 32 @ (d: 8, pc) @ (d: 16, pc) pc-relative @@ a a : 8 memory indirect each instruction can use a subset of the available addressing modes. the data transfer instructions can make use of all addressing modes except pc relative and memory indirect. all arithmetic and logical operations can use the register direct and immediate modes and the bit manipulation instructions use the register direct, register indirect and absolute addressing modes. supporting both array and stack data types, the h8/300h has indirect addressing with either postincrement or predecrement. these modes support byte, word and long word data (+ 1,2 and 4) as shown.
8 register indirect with post-increment or pre-decrement register indirect with post-increment @ ern + register contents op reg 31 0 23 0 1 , 2 or 4 + register indirect with pre-decrement @ ern + register contents op reg 31 0 23 0 1 , 2 or 4 + added value operand size byte 1 word 2 longword 4 three absolute addressing modes are provided using 8, 16 or 24-bit absolute addresses. using the 24-bit address the entire 16mbytes address space is accessible. the 8 and 16-bit absolute address modes assume that the upper byte or word of the address is h'ffff or h'ff respectively. this allows for the efficient address specification for the on-chip i/o area and ram areas which are both placed at the top of the address map. these shortened addresses save significant amounts of code when these areas are accessed.
9 instruction set the h8/300h has an instruction set which suits the combined needs of hll programming and embedded applications. it comprises of 62 instructions, with an emphasis on arithmetic instructions, address manipulation and bit processing. more than half of all instructions have an instruction length of only 2bytes making very compact code. function instruction data transfer mov, push, pop, movtpe, movfpe arithmetic operations add, sub, addx, subx, inc, dec, adds, subs, daa, das, mulxu, divxu, mulxs, divxs, cmp, neg, exts, extu loqic operations and,or,xor,not shift operations shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr bit manipulation bset, bclr, bnot, btst, band, biand, bor, bior, bxor, bixor, bld, bild, bst, bist branch bcc, jmp, bsr, jsr, rts system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop block data transfer eepmov in comparison with the h8/300 cpu most of the data transfer, logical, shift and arithmetic instructions are improved to handle 16 and 32-bit data. new instructions added to the h8/300h include signed multiplication, sign extension, 16-bit branch instructions and a software trap instruction. the following table illustrates the new and improved instructions provided by the h8/300h.
10 instruction datasize byte word long word data transfer mov eepmov (block transfer) arithmetic operations add, sub, cmp, mul u/s div u/s ext. s/u * logical operations and, or, xor, etc. shift and rotate shal, shar, rot, etc. system control push, pop trapa branch bcc d : 16 h8/300 & h8/300h h8/300h * improved addressing mode on h8/300h arithmetic instructions in order to perform complex algorithms such as digital filtering the h8/300h is equipped with powerful arithmetic instructions, including addition and subtraction on 32-bit data and multiplication of 16 x 16-bit data and division of 32 / 16-bit data. multiplication and division are both available as signed and unsigned operations, which eliminate the need for time consuming library calls. the table below gives a guide to the execution speed of various arithmetic instructions with a clock of 16mhz. add 32bit operands 125ns and 32 bit operands 125ns multiply/divide 16bit operands (32bit result, signed) 1.5 m s multiply/divide 16bit operands (32bit result, unsigned) 1.375 m s
11 bit processing in microcontroller applications it is often necessary to manipulate data on a bit by bit basis. a good example would be where an i/o pin needs to be set to switch on a lamp or a solenoid. to meet this demand the h8/300h has 14 separate bit processing instructions which allow the programmer to manipulate bit data very easily. 0 7 0 7 00 0 0 1 0 1 ril 0 instruction: brst ril, rih ril points to a bit position within rih 01 0 0 0 0 0 0 z in ccr bit # 5 = 5 it is also possible to perform boolean algebra on bit data using the carry flag of the ccr register as a bit accumulator. in a microcontroller application it is often necessary to perform a branch depending on the values of two bit flags located in ram or i/o ports. using the boolean operations provided by the h8/300h the first bit can be loaded into the carry flag. then a bitwise logical operation can be executed using the second bit. this sequence would then be followed by a branch depending on the value of the carry flag. another feature of the h8/300h bit processing capability is its ability to access bits indirectly, using the value from a general purpose register as a bit pointer. this mechanism is shown below and is useful for scanning a byte for set or cleared bits.
12 block move instruction another efficient instruction provided by the h8/300h cpu is the eepmov or block data transfer. this is useful when a table stored in rom has to be transferred to ram for manipulation. block sizes up to 64kbytes can be transferred with a single instruction. software interrupt the trapa instruction has been added to the h8/300h cpu. this instructions implements a software interrupt, jumping to a service routine via one of four exception vectors (trapa 0 - 3). this operation can be used to implement fast, space efficient calls to often used sub-routines such as schedulers and other o/s routines. the trapa instruction can also be used as a call to an error handling routine.
13 cpu states / low power modes the h8/300h cpu has four different processing states: program execution, exception handling, bus-released and power-down. in the program execution state the cpu executes normal program instructions in sequence, while the exception handling state is a transient state in which the cpu executes an exception handling sequence in response to a reset, interrupt or other exception. in the bus-released state the external bus has been released to an external bus-master other than the cpu. in the power down mode the cpu is halted to conserve power. the power down modes include three modes: sleep, software standby and hardware standby. these modes are enhanced in the h8/3048 series by adding module standby and clock gearing. low power modes the h8/300h series has been designed to be a microcontroller with high performance and low power dissipation. it therefore can be used in 3v or 5v systems and only consumes 20ma (max.) when operating at 3v and 8mhz. to widen its use in battery operated equipment such as cellular telephones, an impressive set of low power modes are also provided on all devices. sleep mode in this mode the device switches off the clock to the cpu, but all of the on-board peripherals remain active, and register and memory contents are retained. sleep mode is entered via the sleep instruction; the cpu exits this mode whenever an enabled interrupt occurs. a useful application for this mode is to reduce the average power consumed by a system, using a timer to wake the cpu after a period of sleep. once woken, the cpu can process for a period of time and then after loading the timer again the sleep instruction can be executed, again lowering the power consumption. when sleep mode is entered the device's current consumption is reduced by approximately one third over its operating value. software standby mode again, this mode can be entered using the sleep instruction, but in this case the on-chip oscillator is stopped completely, putting the device into software standby. standby current is very low with a maximum value of 5 m a. this is coupled with a data retention voltage of 2v, allowing the microcontrollers internal ram contents to be maintained using just two 1.5v
14 battery cells or possibly a large reservoir capacitor. during software standby mode, the microcontroller maintains the value of the i/o ports, so output ports can be set to the values the system requires during power down, with the knowledge that they will remain stable during software standby mode. to exit from this mode, an external interrupt can be used, and a specialised timer circuit is provided to ensure that the on-chip oscillator has started and is stable before execution of the interrupt service routine begins. hardware standby mode this mode allows the device to be put into the low power mode via an external pin. while in this mode the maximum current consumption is 5 m a and to exit hardware standby the chip must be reset. extra power down support - h8 / 3048 the h8/3048 range incorporates some extra power down options making it an ideal device in many high performance battery driven systems. the first feature is the ability to put individual peripherals into standby mode via software. the control register used for this operation is shown below. pstop - mstop5 mstop4 mstop3 mstop2 mstop1 mstop0 010 0000 initial value: r/w - r/w r/w r/w r/w r/w r/w r/w 0 enable / disable f clock output itu standby sci1 standby scio standby dmac standby refresh controller standby a/d standby this feature makes the h8/3048 an ideal fit into cellular handsets as it mirrors the hardware designers efforts to enable parts of the circuit to be powered down when they are not required.
15 clock gearing another power down feature provided by the h8/3048 is its ability to change the on-chip operating frequency via a software command. this is achieved using a programmable clock divider which allows the clock to be divided by 1, 2, 4 or 8. bit 1 bit 0 divide ratio f = 16 mhz div 1 div 0 0 0 1/1 f = 16mhz 0 1 1/2 f = 8 mhz 1 0 1/4 f = 4 mhz 1 1 1/8 f = 1 mhz clock gearing allows the performance and power dissipation to be changed to suit the system's current mode. for example, when scanning a keyboard or other input device the divide by 8 option could be selected, but once a pressed key is detected the divide by 1 option can be selected to instantly give the device full speed operation.
16
17 exceptions and interrupts exceptions on the h8/300h cpu fall into four categories, reset (highest priority), external interrupts, internal interrupts and trap exceptions. the following table shows the exception vector table for the h8/300h cpu core. exception source vector vector address reset 0 h'0000 to h0003 reserved for system use 1 h'0000 to h'0007 2 h'0008 to h'000b 3 h'000c to h'000f 4 h'0010 to h'0013 5 h'0014 to h'0017 6 h'0018 to h'001b external interrupt (nmi) 7 h'001c to h'001f trap instruction (4 sources) 8 h'0020 to h'0023 9 h'0024 to h'0027 10 h'0028 to h'002b 11 h'002c to h'002f external interrupt irqo 12 h'0030 toh'0033 external interrupt irq1 13 h'0034 to h'0037 external intemipt irq2 14 h'0038 to h'003b external interrupt irq3 15 h'003c to h'003f external interrupt irq4 16 h'0040 to h'0043 external interrupt irq5 17 h'0044 to h'0047 external interrupt irq6 18 h'0048 to h'004b external interrupt irq7 19 h'004c to h'004f lnternal interrupts 20 to 60 h'0050 to h'0053 to h'00f0 to h'00f3
18 trap exceptions when the trap instruction is executed, the program will start executing from the location specified in the relevant vector. the trap instruction has four vectors as specified by its argument. this exception can be used as an efficient mechanism for calling operating system functions, as it takes only 2 bytes to execute a trap operation, compared to 4 bytes for a bsr and 8 bytes for a jsr. interrupt controller the h8/300h interrupt controller (intc) can be operated in two modes, either maintaining compatibility with the standard h8/300 intc, or in a more advanced mode. h8 / 300 compatible mode in this mode, the acceptance of maskable interrupts is controlled by the i bit in the ccr. if i is set then all interrupts are disabled and if i is cleared then all interrupts are enabled. when an interrupt is accepted the intc automatically sets the i bit, thus disabling any other maskable interrupt for the duration of the interrupt service routine (isr), unless it is cleared by the user's code. h8 / 300h advanced mode to increase the power of the interrupt controller, an extra interrupt status bit is included in the condition code register, known as the ul or user interrupt bit. this extended operation allows the user to specify raised priority interrupt sources, which are capable of interrupting a low priority isr which is already running. the priority of individual interrupt sources is programmed in a number of interrupt priority registers (ipr). external interrupts all the h8/300h devices include several external interrupts, including one non maskable interrupt (nmi). nmi can be programmed to be activated on either the rising or falling edge and the standard external interrupts can be programmed to recognise either a low level or a low going edge. interrupt vectors to speed up the processing of interrupts, every interrupt source has its own vector. for example, for each serial port there are separate vectors for transmit, receive and error interrupts. therefore, the isr does not need to poll a peripheral block to find the source of any interrupt.
19 interrupt response time interrupts are responded to rapidly on the h8/300h. when code and data are both located in the on-chip memory, then the isr will be reached within 2.6 microseconds (worst case) at 16mhz. if this is coupled with the individual vector structure provided by the h8/300h, the isr can be performing useful work very quickly indeed. the table below shows how fast h8/300h responds to interrupts in several configurations. external memory 8-bit bus 16-bit bus no item on-chip memory 2states 3 states 2 states 3 states 1 interrupt priority decision 2 2 *1 2 *1 2 *1 2 *1 2 maximum number of states until end of current instruction 1 to 23 1 to 27 1 to 31 *4 1 to 23 1 to 25*4 3 saving pc and ccr to stack 4 4 12 *4 4 6 *4 4 vector fetch 4 8 12 *4 4 6 *4 5 instruction prefetch *2 4 8 12 *4 4 6 *4 6 lnternal processing *3 4 4 4 4 4 total (clocks) 19 to 41 27 to 53 43 to 73 19 to 41 25 to 49 notes: 1. one state for internal interrupts 2. prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt service routine 3. lnternal processing after the interrupt is accepted and internal processing after prefetch 4. the number of states increases if wait states are inserted in external memory access
20
21 on-chip memory often, due to its power and ability, a h8/300h device will be used in applications where the program size is very large. at first glance, these large programs appear to preclude using any microcontroller in single chip mode. but large programs place no restriction on the h8 / 300h family, as unparalleled sizes of on-chip program and data memory are available, even in its smallest package. for example the h8 / 3048 with 128k of prom / rom / flash and 4k of ram in a single chip, 100-pin device measuring just 17.2 mm across its pins. new variants of the h8 / 300h family are also under development. rom ram 0 16k 32k 48k 64k 96k 128k 192k 256k 512 byte 3001 3002 3003 3030 1k 3031 2k 3004 3040 3044 3041 3032 3042 3045 4k 3005 3047 3033 3048 3048 flash 3034 3035 bold products are also available as ztat (otp). now available! h8/3035 with 256k rom/otp and 4k ram
22
23 flash memory (f-ztat) together with the flash-derivatives in other microcontroller families, hitachi offers the worlds best line up of microcontrollers with on-chip flash currently in full production. hundreds of customers world wide have taken advantage of our flash based microcontrollers in their designs, about one third in industrial and automotive applications, approximately one fourth each in consumer and office automation and the remainder in telecommunications. now available! evaluationboard for h8/3048f the advantages of flash based microcontrollers include: end of line programming allows flexibility in the software until shipment software flexibility during production ramp up and development allows easy and fast update in the field without the need to open the equipment allows software updates even remotely, e.g. via modem/phone line fast response to changing customer requirements non volatile storage of data and parameters
24 technology flash memory is programmed by applying a high gate-drain voltage that draws hot electrons generated in the vicinity of the drain into a floating gate. the threshold voltage of a programmed cell is therefore higher than that of an erased cell. cells are erased by grounding the gate and applying a high voltage to the source, causing the electrons stored in the floating gate to tunnel out. a flash memory cell is read like an eprom cell, by driving the gate to the high level and detecting the drain current, which depends on the threshold voltage. programming takes 50 m s/byte and erasing 1s per block or for the full flash memory. hitachi's h8/3048f offers full speed operation (16mhz/5v and 8mhz/3v), block division into 8 small (512byte) and 8 large blocks (12k and 16k) and various ways to program the h8/3048f's flash memory. these modes are selected by pins on reset and allow on-board programming: user program mode: in user program mode the flash memory can be erased and programmed under control of an user program. in this mode all the resources of the h8/3048f can be used except the flash memory, as reading from the flash memory is not possible during erasing or programming. boot mode: boot mode allows the user to erase and program the flash memory via the serial interface sci1. this is possible even if the microcontroller contains no user software, i.e. it allows in-circuit-programming of new (empty) devices. prom mode: the h8/3048f can also be programmed using general purpose prom programming equipment. the h8/3048f is inserted in the programmer using a socket adapter available from hitachi. other technical characteristics of hitachi's on-chip flash memory include: security mechanism against malicious access makes theft of code virtually impossible. accidental erase or write impossible without vpp being present. 100 erase/write cycles guaranteed with higher specification under preparation.
25 bus state controller (bsc) as one of the key reasons for using the h8/300h is the 16mbytes linear address space, it is likely that it will be used in a system with a large quantity of memory. consequently, the h8/300h cpu core is supported by a powerful bus state controller (bsc) that allows the memory to be configured in the system in the most appropriate way. the h8/300h bsc is able to configure eight memory areas with their own independent attributes. in the advanced modes, these areas are either 256kbytes (1 mbytes mode) or 2mbytes (16mbytes mode) in size. the attributes which can be set for each area are the bus width, the number of cycles for each external access and the wait state mode used. bus width (bits) access cycles size (max.) sram 8/16 2..6 16mb eprom 8/16 2..6 16mb psram 8/16 2..6 16mb dram 16 3..6 2mb when a memory area is initialised into the 3-state access cycle mode, the wait state controller can be activated for this area to allow slow devices to be connected to the bus of the h8/300h. there are four wait modes available: the programmable wait mode, pin auto wait mode and the pin wait modes 0 and 1. wait state controller mode operation pin wait mode 0 two wait states are inserted whenever the wait pin is sampled low. the wait state controller is otherwise disabled for memory areas so specified. pin wait mode 1 the number of wait states programmed in the wsc are inserted and then the wait pin is sampled. if it is low further wait states are inserted. pin auto-wait mode if the wait pin is low when sampled the number of wait states programmed in the wsc are inserted and then the bus cycle is terminated. programmable wait mode for every access to the specified 3-state access area, the number of wait states programmed in the wsc are inserted automatically. combining the bsc with the on-chip refresh controller, allows the h8 / 300h to be interfaced to a wide range of memory types, including dram, sram, psram and eprom with the minimum of external logic. this function extends to the generation of chip selects corresponding to the memory area being accessed.
26 dram and psram interface to provide a large area of ram, the most cost effective memory type to use is dram. however, normally in an embedded system the external devices required to interface with dram often causes designers to use sram as the lowest cost system option. to allow designers to utilise the full benefit of using dram in their system, the h8/300h has been equipped with a bus interface which can couple directly to dram with the minimum of external components. this has been achieved by incorporating the logic required to produce the dram interface signals and a refresh controller into the bsc. for example, the figure below shows the connection of a h8/3003 to a 4-mbit dram. h8/3003 a 18 a 17 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 cs 3 rd hwr lwr d 15 to d 0 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 ras cas uw lw i/o 15 to i/o 0 oe a 0 2 we 4-mbit dram with 10-bit row address, 8-bit column address, and x 16-bit organization the h8/300h supports 1mbit and 4mbit dram (2we or 2cas) in 16-bit wide configurations. the refresh controller can be programmed to produce a wide variety of refresh intervals, and the dram controller can put the dram into self refresh mode whenever the software standby mode is selected.
27 chip select generation the bsc on the h8/3003, h8/3002 and h8/304x devices can be used to generate chip select signals for different memory areas. these chip selects have the added benefit of becoming active at the same time as the address becomes valid, thus removing any decode delay.
28
29 direct memory access controller (dmac) to complement a cpu which provides high performance operation for complex algorithms and an address space which can handle large data structures and program modules, the addition of a direct memory access controller (dmac) on-chip will significantly increase the performance of the system. the dmac will allow the utilisation of the whole cpu performance for the system's algorithms, while repetitive but important data transfer can be done via dma. any external or internal interrupt that initiates a data transfer can be completely serviced by the dma without any interrupts being handled by the cpu. this drastically reduces the cpu overhead needed for interrupt handling. when used with other on-chip peripherals such as the itu, the dmac allows the control of real time inputs and outputs, or it can be used to service the serial interfaces. the basic h8/300h dmac module incorporates four channels. however, the h8/3003 actually provides eight channels. each channel in the dmac module can be utilised to perform transfers between memory and i/o, while 2 channels need to be combined for memory to memory transfers. byte and word transfer are possible in all available operating modes. internal address bus address buffer module data bus arithmetic-logic unit internal interrupts imia0 imia1 imia2 imia3 txi0 rxi0 dreq0 dreq1 tend0 tend1 control logic dend0a interrupt signals dend0b dend1a dend1b dtcr0a dtcr0b dtcr1a dtcr1b data buffer internal data bus channel 0 channel 0a channel 0b channel 1a channel 1b channel 1 mar0a ioar0a etcr0a mar0b ioar0b etcr0b mar1a ioar1a etcr1a mar1b ioar1b etcr1b legend dtcr: data transfer control register mar: memory address register ioar: i/o address register etcr: execute transfer count register
30 short address mode in this mode an 8-bit source address and 24-bit destination address (or vice versa) are used. during the transfer the 8-bit address (which points to an i/o register) is fixed while the 24-bit address may change according to the way the channel has been initialised. in this mode dma transfers are initiated by interrupts from the timer block, the serial port or via an external signal. one byte or word of data is transferred per request and the 24-bit address incremented by one or two after each transfer. if a fixed memory address is required, then the channel can be put into an idle mode, where the 24-bit address will not increment. up to 64k transfers can be performed before an interrupt is signaled to the cpu. the dma channel can also be set to automatically repeat up to 256 transfers continuously, with the dma channel being reinitialised and restarted after the specified number of transfers has been performed. this is useful when cyclic data such as a control pattern for a stepper motor has to be transferred. full address mode to perform memory to memory transfers the full address mode can be used. here, the source and destination addresses are 24-bits wide each, and therefore memory to memory transfer can be performed between any areas of the full 16mbytes address space. dma transfers can be initiated by software command, external signals or interrupts from the timer block. this mode allows either a single transfer to occur per request, or for a block of data to be moved. in the block mode, the dmac can be set up in a burst mode, taking over the bus from the processor until all the transfers are complete, or in a cycle steal mode where the processor and the dmac share the bus. dmac interrupts the dmac can be set up to provide an interrupt per request, or to only interrupt the processor when it has performed a programmed number of transfers. dmac modes the dmac provides a choice of short and full addressing modes, which allow the dma to be adapted according to system requirements.
31 address register length transfer mode activation source destination short address mode io mode transfers 1 byte or 1 word per request increments or decrements the memory address by 1 or 2 executes 1..65536 transfers compare match/input capture a interrupts from itu channels 0..3 transmit data empty interrupt from sci 24 8 idle mode transfers 1 byte or 1 word per request holds the memory address fixed executes 1..65536 transfers receive data full interrupt from sci external request 8 24 repeat mode transfers 1 byte or 1 word per request increments or decrements the memory address by 1 or 2 executes a specified number (1..256) of transfers then returns to the initial state and continues 24 8 full address normal mode auto request ? retains the transfer request externally ? executes a specified number (1..65536) ? of transfers continuously ? selection of burst mode or cycle steal mode external request ? transfers 1 byte or 1 word per request ? executes 1..65536 transfers auto request external request 24 24 block transfer transfers 1 block of a specified size per request executes 1..65536 transfers allows either the source or the destination to be a fixed block area block size can be 1..256 byte or word compare match/input capture a interrupt from itu channels 0..3 external request 24 24
32
33 integrated timer unit (itu) in many microcontroller based systems, very specialised timer functions are required. often these timer functions are produced in a user developed asic device, because the timers provided by the microcontroller do not meet the performance required by the designer. the timer unit on the h8 / 300h has been designed to allow maximum flexibility in its use, therefore allowing the designer to get the timer configuration required without resorting to an external timer device. bus interface module data bus legend toer: timer output master enable register (8 bits) tocr: timer output control register (8 bits) tstr: timer start register (8 bits) tsnc: timer synchro register (8bits) tmdr: timer mode register (8 bits) tfcr: timer function control register (8 bits) 16-bit timer channel 4 16-bit timer channel 3 16-bit timer channel 2 16-bit timer channel 1 16-bit timer channel 0 todr tocr tstr tsnc tmdr tfcr on-chip data bus clock selector control logic counter control and pulse i/o control unit imia0 to imia4 imib0 to imib4 ovi0 to ovi4 tclka to tclkd ? , ? /2, ? /4, ? /8 tocxa , tocxb 44 tioca to tioca 04 tiocb to tiocb 04 the itu consists of five separate 16-bit timer channels, each of which can be clocked from an internal derivative of the system clock ( f , f /2, f /4 and f /8) or from an external pin. if the f clock option is selected, then the minimum resolution of the timer is 62.5ns ( f = 16mhz). the standard timer functions provided by the itu include ten general registers (gr), which can be used as output compares or input captures. thus the complete timer block provides up to ten pulse inputs or outputs. a further four 16-bit buffer registers (br) reduce the overhead placed on the cpu when servicing the timer block.
34 item channel 0 channel 1 channel 2 channel 3 channel 4 clock sources internal clocks: f , f /2, f /4, f /8 external clocks: tclka, tclkb, tclkc, tclkd, selectable independently general registers (output compare/ input capture registers) gra0, grb0 gra1, grb1 gra2, grb2 gra3, grb3 gra4, grb4 buffer registers - - - bra3, brb3 bra4, brb4 input/output pins tioca0 tiocb0 tioca1 tiocb1 tioca2 tiocb2 tioca3 tiocb3 tioca4, tiocb4 output pins ---- tocxa4, tocxb4 counter clearing function gra0/grb0 compare match or input capture gra1/grb1 compare match or input capture gra2/grb2 compare match or input capture gra3/grb3 compare match or input capture gra4/grb4 compare match or input capture compare match output 0 ????? 1 ????? toggle ?? - ?? input capture ????? synchronization ????? pwm mode ????? reset-synchronized pwm mode ----- complementary pwm mode --- ?? phase counting - - ? -- buffering - - - ?? legend ? :available -: not available
35 output compare functions to create output waveforms or timed interrupts, the itu provides up to 10 output compare registers. the output compares work by producing an output of a pre-programmed level and/or an interrupt when the value in the counter matches the value stored in one of the output compare registers. the events that can be initiated by these compare matches are transitions on an output pin (to high, to low or toggle), a cpu interrupt (used for software timing functions), clearing the counter and the triggering of a dma channel. channels 3 and 4 allow to produce a pulse with duration down to one clock cycle (62.5ns at 16mhz). a combination of the output compare function with the dmac and the tpc (a peripheral explained later) can be used to control stepper motors very easily. input capture functions the itu provides up to 10 channels of input capture. in this mode the timer can be set up so that a transition on an input pin causes the value currently in the count register to be transferred into a capture register, thus time stamping that particular event. the itu can be set to capture rising edges, falling edges and either of these. if required the timer unit can also clear the timer when the programmed external event occurs. the two buffer registers (bra and brb) provided in timer channels 3 and 4 can be used to buffer input time stamps. this allows events which occur very close together to be time stamped using one capture pin. this feature can also be used to measure the width of an incoming pulse, by programming the capture input to be triggered on both the rising and falling edges. by using input captures to measure the timing of external signals, very accurate measurements of variables such as frequency can be taken. the user can be sure that the accuracy of the measurement is not compromised by interrupt response time, as it is entirely a hardware driven facility. it is also possible to initiate dma transfers when an input capture event occurs. this allows time stamps to be automatically placed in memory via the dma controller, without needing to interrupt the cpu. timer synchronisation to allow timer channels in the itu to be used in synchronisation, it is possible to set up two or more timers so that they are simultaneously written to via software and cleared by compare matches or input captures. when timer channels are put into this mode then their input and output events are also synchronised.
36 pwm operating modes the pwm (pulse width modulation) modes of the itu are described in the following diagrams. tioca write to gra write to gra time gra grb h'00 counter cleared by compare match tcnt value standard pwm mode each timer channel can be programmed to produce a single phase pwm output.thus the itu can output up to five separate channels of pwm. in this mode gra controls the time when the pin goes high, and grb when the pin goes low. either gra or grb can be set to clear the counter, thus setting the frequency of the pwm output. the table below shows the pwm frequencies which can be obtained against device clock speed and output resolution. pwm resolution 16 mhz 12 mhz 10 mhz 8 mhz 6 mhz 14-bit 976.5 hz 732.7 hz 610 hz 488 hz 365 hz 12-bit 3.9 khz 2.9 khz 2.4 khz 2 khz 1.5 khz 10-bit 15.6 khz 11.7 khz 9.7 khz 7.8 khz 5.8khz 9-bit 31.2 khz 23.4 khz 19.5 khz 15.6 khz 11.7 khz 8-bit 62.4 khz 46.9 khz 39 khz 31.3 khz 23.4 khz 7-bit 124.8 khz 93.8 khz 78 khz 62.5 khz 46.8 khz
37 ac motor control outputs to provide the pwm signals required to drive ac machines, the itu provides two further pwm modes: complementary 6-phase pwm and reset synchronised 6-phase pwm. the main differences between these two modes are the transition points for the outputs and the provision of dead time between the phase outputs. complementary 6-phase pwm in this mode channels 3 and 4 are combined to produce three pairs of non-overlapping pwm waveforms, as described in the figure h8/300h pwm modes. as can be seen from this figure, in this mode tcnt3 and tcnt4 act as up/down counters, counting down from the point set by the compare match tcnt3 and gr3 and counting up from the point at which tcnt4 underflows. tiocxb4 downcounting starts at tiocb4 tocxa4 tioca4 tiocb3 tioca3 up counting starts when tcnt4 underflows time h'0000 grb4 gra4 grb3 tcnt4 tcnt3 tcnt3 and tcnt4 values the pwm waveforms are produced from compare matches with the general registers grb3, gra4 and grb4. using this mechanism, only three registers need to be reloaded to change the modulation ratio, keeping the cpu overhead to a minimum. in an ac motor control system, it is necessary to insert some deadtime between the switching of the complementary phases to ensure that no short circuit condition occurs through the two drivers. the itu supports this function using the difference in value between the two timer channels used. thus a totally programmable deadtime is supported in this mode.
38 tocxb4 counter cleared by compare match with gra3 tiocb4 tocxa4 tioca4 tiocb3 tioca3 time h'0000 grb4 gra4 grb3 tcnt3 values gra3 reset synchronised pwm this output mode is shown in the figure h8/300h pwm modes and it provides three pairs of complementary pwm waveforms, all having one common waveform transition point. in this mode tcnt3 counts up until it is cleared by a match with gra3. the output pins toggle at compare matches between grb3, gra4, grb4 and tcnt3 and they all toggle when tcnt3 is cleared. phase counting mode this mode finds use in servo control systems, where the position and speed feedback comes from a 2- phase quadrature encoder. in this type of encoder the waveforms output change their phase relationship depending on the direction of motion.
39 time counter value count up count down timer counter 2 tclk1 tclk0 tclk1 and tclk0 are signals provided by a 2-phase quadrature encoder. the value of timer counter 2 reflects the position. note: this mode is available only for timer counter 2 tclk0 tclk1 low high high low high low low high countdown countup count condition: count all edges by utilising the phase counting mode on the itu, tcnt2 will count up or down depending on the phase of the incoming signals. therefore, the value of tcnt2 will reflect the positional changes experienced by the encoder. this facility removes the requirement for extra hardware or interrupt handlers for position monitoring. in this mode the comparators of channel 2 can also be used to generate interrupts, for example when a certain position is reached. itu interrupts the itu can produce a total of 15 interrupts. this comprises 3 per channel, one for each general register and an overflow. each interrupt has its own vector, making it unnecessary to poll flags, thus enabling fast reaction by the cpu.
40
41 timing pattern controller (tpc) this peripheral can simultaneously output up to 16 waveforms, using a strobe signal produced by the itu. it is useful for generating the necessary waveforms for driving stepper motors. legend tpmr: tpc output mode register tpcr: tpc output control register nderb: next data enable register b ndera: next data enable register a pbddr: port b data direction register paddr: port a data direction register ndrb: next data register b ndra: next data register a pbdr: port b data register padr: port a data register internal data bus ndrb ndra pbdr padr pulse output pins, group 3 pulse output pins, group 2 pulse output pins, group 1 pulse output pins, group 0 tp 15 tp 14 tp 13 tp 12 tp 11 tp 10 tp 9 tp 8 tp 7 tp 6 tp 5 tp 4 tp 3 tp 2 tp 1 tp 0 control logic paddr ndera tpmr pbddr nderb tpcr itu compare match signals the main registers of the tpc are the next data registers (ndra~d). these registers are each 4- bits wide and contain the next data which will be transferred into the port data registers padr and pbdr. this data is transferred using a strobe signal generated by the selected timer channel output compare. a separate timer channel can be specified to synchronise each group of 4-bits. one of the main applications for this peripheral is the control of multiple stepper motors; if used in conjunction with the on-chip dma controllers then this control can be performed with very little cpu supervision. stepper motor control with the tpc a diagram showing how stepper motor control can be performed using the itu, tpc and dmac is shown below. in this example a two phase stepper motor is being driven, using complementary transistors. it is therefore necessary to provide a dead time between the switching of the phases to eliminate any short circuit conditions between the high side and low side drivers.
42 memory output pattern data table step pulse period data table itu clock ocra ocrb dma channel 1 data flow trigger dma channel 0 ndra pbdr tpc pins motor control pulses ocra holds non-overlap time ocrb holds step pulse time using compare matches from the itu to stimulate the dmac, new pattern data is provided to the tpc. this pattern data represents the next phase drive pattern required, and is stored in a memory table. the dmac uses its memory to i/o function to transfer this data on each compare match. the tpc also uses the stimulus from the itu to transfer the contents of the ndr to the port. using a tpc mode where transitions on the port from 0 to 1 (i.e. switching on a phase) are only made on compare match a, a dead time, equal to the value in gra, is inserted.
43 revolutions constant acceleration deceleration = cpu intervention required when controlling a stepper motor, providing the phase patterns onto the port pins is only part of the story. it is also necessary to modify the time between new patterns being output to allow acceleration and deceleration of the motor as shown by the velocity profile. when the tpc, itu and dmac are working together, the acceleration and deceleration phases, as well as the steady speed phase can be controlled with minimal cpu overhead. the cpu need only get involved when a transition from one phase to another is made. this is achieved by using a second memory to i/o dma channel to reload the timer compare register after each new pattern has been output. again the dmac can take the next step period data from a table of values stored in the memory of the system. therefore, by providing a table of increasing or decreasing values the motor can be decelerated or accelerated with no cpu intervention. the flexibility of the h8/300hs stepper motor control functions will even allow multiple motors to be controlled simultaneously by one device. the figure shows examples of the stepper motors which can be controlled, and contrasts the resources required with the amount of resource available on the h8/3003.
44 2-phase 1-excitation 2-phase 2-excitation 2-phase 1-2-excitation 5-phase 5-excitation dmac tpc itu 2-phase 1-excitation 2-phase 2-excitation 2-phase 1-2-excitation 5-phase h8 / 3003 total 2ch 4-bits 1ch 2ch 4-bits 1ch 2ch 4-bits 1ch 2ch 5-bits 1ch 8ch 16-bits 5ch 2 -phase i-excitation 2-phase 2-excitation 2-phase 1-2-excitation 5-phase h8 / 3003 total dmac 2 ch 2 ch 2 ch 2 ch 8 ch tpc 4-bits 4-bits 4-bits 5-bits 16-bits itu 1 ch 1 ch 1 ch 1 ch 5 ch
45 watchdog timer (wdt) often, a watchdog timer is a very important feature in any embedded application. it is used to ensure that any mishap in the system (such as a noise induced software crash) is rectified as quickly as possible. the principle behind a watchdog timer is very simple - a counter is constantly counting upwards, and correctly operating software ensures that this counter never overflows by continuously resetting the count. if the software crashes and the counter overflows, the watchdog barks and sends some stimulus to the microcontroller (normally a reset) to restart system operations in a controlled manner. all h8/300h devices are equipped with a timer, which can be used either as a watchdog or as an interval timer. its bark is a reset if it is used as a watchdog. internal clock sources ? /2 ? /32 ? /64 ? /128 ? /256 ? /512 ? /2048 ? /4096 clock selector tcsr tcnt read/ write control internal data bus clock interrupt control overflow (interval timer) interrupt signal rstcsr reset control reset (internal, external) legend tcnt: timer counter tcsr: timer control/status register rstcsr: reset control/status register
46
47 serial communications interface (sci) this form of communication has many uses in microcontroller applications, such as interdevice communications, diagnostics, host communication, and even as an interface to peripherals. all h8/300h devices are equipped with at least one and very often two channels of serial communication interface (sci). these channels can be used for either synchronous or asynchronous communications. this type of sci is standard across the h8/300h range. as shown in the block diagram each sci channel has its own integral baud rate generator, so many baud rates can be produced from the microcontroller's internal clock, without using any other timers. legend rsr: receive shift register rdr: receive data register tsr: transmit shift register tdr: transmit data register smr: serial mode register scr: serial control register ssr: serial status register brr: bit rate register txi bus interface internal data bus rxi eri transmit/ receive control external clock module data bus rdr tdr rsr tsr rxd txd ssr smr scr parity generate parity check sck brr baud rate generator /4 /16 /64 clock tei as well as using the integral baud rate generator, each sci can be configured to use an external serial clock. to allow back to back transmission or reception of serial data, the sci has double buffered transmit and receive shift registers. the h8/300h serial ports also support multiprocessor communications using a master slave configuration in addition to the standard modes. in this mode, communication between devices is performed using an additional multiprocessor bit (mpb) which is added to the data transmitted. this bit is used to differentiate between data
48 frames and address frames. thus, any frame sent from the master with the mpb set to one can be used to activate the required slave. transmitting processor receiving processor a processor b receiving processor c receiving processor d receiving (id = 01) (id = 02) (id = 03) (id = 04) serial data h'01 h'aa (mpb = 1) (mpb = 0) id-sending cycle: receiving processor address data -sending cycle: data sent to receiving processor specified by id serial communication line legend mpb: multiprocessor bit slave devices on this network will only produce a receive interrupt when a frame is received with the mpb set, so the interrupt handler can check the address which has been transmitted. receive data errors are trapped using three error conditions -overflow,framing and parity. these three errors are indicated via one interrupt vector and three status flags in the serial status register.
49 analogue to digital converter (adc) in many microcontroller based systems, some way of measuring analogue electrical values is necessary.with this in mind, all members of the h8/300h family are equipped with a 10-bit a/d converter. module data bus legend adcr: a/d control register adcsr: a/d control/status register addra: a/d data register a addrb: a/d data register b addrc: a/d data register c addrd: a/d data register d an 0 bus interface on-chip data bus an 1 an 2 an 3 an 4 an 5 an 5 an 7 successive- approximations register 10-bit d/a av cc av ss + _ analog multi- plexer control circuit sample and hold circuit comparator /8 /16 adi adtrg v ref addra addrb addrc addrd adcsr adcr the converter works using a successive approximation algorithm and conversions take 138 states (or 8.6 m s if f - 16mhz). up to 8 inputs can be converted; this is achieved using an 8 channel multiplexer between the input port and the a/d. a sample and hold capacitor is used to ensure that once a conversion begins, a change of the input value will not be reflected in a different conversion result. as well as being able to perform single conversion (where only one channel is converted), the h8/300h a/d converter can also be used to scan up to four channels. to support this mode of operation, four a/d result registers are provided. once the scan mode is selected, each channel specified is converted sequentially with the conversion value being stored in the appropriate result register. this mode of operation allows the user software to sample the current analogue value of an input by simply reading the appropriate data register.
50 digital to analogue converter (dac) the h8/304x device incorporates an 8-bit digital to analogue converter which has a maximum conversion time of 6.2ms ( f = 16mhz). two outputs are provided and multiplied with the analogue to digital inputs. the output voltage range is from 0v through to the a/d reference voltage.
51 h8/300h summary in the previous chapters we have given an overview as to why h8/300h gives the designers the technical benefits that are demanded by todays applications. their purpose was to give you enough insight into the features of the h8/300h family to see how you can benefit from the performance, the rich set of peripherals and the memory options available. to summarize this: high performance cpu with architecture tailored for high level language software development many low power, low voltage options memory line up from 16k to 256k rom and 512byte to 4k ram, also version with 128k flash very powerful and sophisticated peripherals designed to offload the cpu and hence to increase system performance full european technical and tool support the following chapters are provided for you to select the right derivative for your application from the h8/300h family.
52 selection guide (rom-less) type no. h8/3001 h8/3002 h8/3003 h8/3004 h8/3005 ram (byte) 512 512 512 2k 4k vcc (v) / clock (mhz) 4.5-5.5/16 3.15-5.5/13 3.0-5.5/10 2.7-5.5/8 4.5-5.5/16 3.0-5.5/10 2.7-5.5/8 4.5-5.5/16 3.0-5.5/10 2.7-5.5/8 4.5-5.5/16 4.5-5.5/18 3.0-5.5/10 2.7-5.5/8 4.5-5.5/16 4.5-5.5/18 3.0-5.5/10 2.7-5.5/8 address space (byte) 16m 16m 16m 16m 16m external data bus (bit) 8/16 8/16 8/16 8 8 itu (16-bit timer) 55555 watchdog timer - 1111 dmac memory to/from i/o memory to memory - - 4 2 8 4 - - - - sci (async/sync) 12211 tpc (bit) 12 16 16 - - adc 10 bits external trigger input 4 - 8 yes 8 yes 8 yes 8 yes refresh controller - yes yes - - chip select pins - 4 8 - - interrupts internal external level 20 4 30 7 34 9 21 6 21 6 i/o 32 46 58 32 32 package fp-80a tfp-80c fp-100a* fp-100b tfp-100b fp-112 tfp-80c fp-80a tfp-80c fp-80a * for availability of fp-100a please contact hitachi or an authorized distributor
53 selection guide (rom/ztat/flash) type no. h8/3030 h8/3031 h8/3032 h8/3040 h8/3041 h8/3042 rom (byte) 16 k 32 k 64 k 32 k 48 k 64 k ram (byte) 512 1 k 2 k 2 k 2 k 2 k ztat(otp) - - yes - - yes vcc (v) / clock (mhz) note 1 5/16 2.7-5.5/8 5/16 2.7-5.5/8 5/16 2.7-5.5/8 5/16 2.7-5.5/8 5/16 2.7-5.5/8 5/16 2.7-5.5/8 address space (byte) 1 m 1 m 1 m 16m 16m 16m external data bus (bit) 8 8 8 8/16 8/16 8/16 itu (16-bit timer) 5 5 5 5 5 5 watchdog timer 1 1 1 1 1 1 dmac memory to/from i/o memory to memory - - - - - - 4 2 4 2 4 2 sci (async/sync) 1 1 1 2 2 2 tpc (bit) 16 16 16 16 16 16 adc 10 bits external trigger input 8 yes 8 yes 8 yes 8 yes 8 yes 8 yes 8-bit dac (channels) - - - 2 2 2 refresh controller - - - yes yes yes chip select pins - - - 4 4 4 interrupts internal external level 21 6 21 6 21 6 30 7 30 7 30 7 i/o 63 63 63 78 78 78 package fp-80a tfp-80c fp-80a tfp-80c fp-80a tfp-80c fp-100a* fp-100b tfp-100b fp-100a* fp-100b tfp-100b fp-100a* fp-100b tfp-100b note 1: 5v with10% tolerance * for availabilty of fp-100a please contact hitachi or an authorized distributor now available up to 18mhz at 5v: h8/3035 256k rom/otp h8/3034 192k rom h8/3033 128k rom all with 4k ram
54 selection guide (rom/ztat/flash) type no. h8/3044 h8/3045 h8/3047 h8/3048 h8/3048f rom (byte) 32 k 64 k 96 k 128 k 128 k ram (byte) 2 k 2 k 4 k 4 k 4 k ztat(otp) - - - yes flash vcc (v) / clock (mhz) note 1 5/16 5/18 3.3/13 2.7/8 5/16 5/18 3.3/13 2.7/8 5/16 5/18 3.3/13 2.7/8 5/16 5/18 3.3/13 2.7/8 5/16 2.7-5.5/8 address space (byte) 16m 16m 16m 16m 16m external databus (bit) 8/16 8/16 8/16 8/16 8/16 itu (16-bit timer) 5 5 5 5 5 watchdog timer 1 1 1 1 1 dmac memory to/from i/o memory to memory 4 2 4 2 4 2 4 2 4 2 sci (async/sync) 2 2 2 2 2 tpc (bit) 16 16 16 16 16 adc 10 bits external trigger input 8 yes 8 yes 8 yes 8 yes 8 yes 8-bit dac (channels) 2 2 2 2 2 smart card i/f yes yes yes yes yes refresh controller yes yes yes yes yes chip select pins 8 8 8 8 8 interrupts internal external level 30 7 30 7 30 7 30 7 30 7 i/o 78 78 78 78 78 package fp-100b tfp-100b fp-100b tfp-100b fp-100b tfp-100b fp-100b tfp-100b fp-100b tfp-100b note 1: 5v with10% tolerance
55 h8/3001 series md 0.10 2.70 -0.16 +0.20 0.10 3.05 max 0.80 0.30 1.60 0.17 +0.08 -0.05 0-5 0.65 21 20 1 40 41 14.0 60 61 80 0.30 + 0.10 - 0.12 o 17.2+ 0.3 - 0.50 21 20 1 40 41 12.0 60 14.0 0.2 61 80 0.20 0.05 0.10 14.0 0.2 17.2 0.3 0.10 0.17 0.05 0-5 o 0.00 min 0.20 max 1.20 max 1.00 0.50 0.10 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 a 0 p9 /sck/irq 4 4 p9 /r x d p9 /t x d 2 0 av ss av cc pa /tp /tclka 0 0 pa /tp /tclkb 1 1 pa /tp /tioca /tclkc 2 2 pb /tp /tioca 0 83 pb /tp /tiocb 1 93 pb /tp /tioca 2 10 4 pb /tp /tiocb 3 11 4 pa /tp /tioca /a 4 41 23 pa /tp /tiocb /a 5 51 22 pa /tp /tioca /a 6 62 21 pa /tp /tiocb /a 7 72 20 p7 /an 0 0 p7 /an 1 1 p7 /an 2 2 p7 /an 3 3 0 pa /tp /tiocb /tclkd 2 2 0 p4 /d 0 0 p4 /d 1 1 p4 /d 2 2 p4 /d 3 3 p4 /d 4 4 p4 /d 5 5 p4 /d 6 6 p4 /d 7 7 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 v ss v ss v ss v cc lwr p8 /irq 0 p6 /back 2 0 p8 /irq 1 1 p6 /breq 1 p6 /wait 0 hwr rd as nmi res o xtal extal md md stby / 0 1 2 clock osc. h8/300h cpu data bus port 4 bus controller data bus (lower) data bus (upper) address bus interrupt controller ram 512 bytes 16-bit integrated timer-pulse unit (itu) programmable timing pattern controller (tpc) serial communication interface (sci) x 2 channels a/d converter port b port a port 7 port 8 port 6 address bus port 9 v cc
56 h8/3002 series md 0.10 2.70 -0.16 +0.20 0.12 3.05 max 0.50 0.20 1.0 0.17 +0.08 -0.05 0-10 0.50 26 25 1 50 51 14.0 75 76 100 0.20 + 0.10 - 0.08 o 16.0+ 0.3 - 0.50 26 25 1 50 51 14.0 75 16.0 0.2 76 100 0.20 0.05 0.08 16.0 0.2 16.0 0.3 0.10 0.17 0.05 0-5 o 0.00 min 0.20 max 1.20 max 1.00 0.50 0.10 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 a 0 av ss av cc pa /tp /tioca /tclkc 2 2 pb /tp /tioca 2 10 4 pb /tp /tiocb 3 11 4 pb /tp /tocxa 4 12 4 pb /tp /tocxb 5 13 4 pa /tp /tioca /a 4 41 23 pa /tp /tiocb /a 5 51 22 pa /tp /tioca /a 6 62 21 pa /tp /tiocb /a 7 72 20 p7 /an 0 0 p7 /an 1 1 p7 /an 2 2 p7 /an 3 3 0 pa /tp /tiocb /tclkd 3 3 0 p4 /d 0 0 p4 /d 1 1 p4 /d 2 2 p4 /d 3 3 p4 /d 4 4 p4 /d 5 5 p4 /d 6 6 p4 /d 7 7 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 v ss v ss v ss v ss lwr p8 /rfsh/irq 0 p6 /back 2 0 p6 /breq 1 p6 /wait 0 hwr rd as nmi res o xtal extal md md stby / 0 1 2 clock osc. h8/300h cpu data bus port 4 bus controller data bus (lower) data bus (upper) address bus interrupt controller ram 512 bytes 16-bit integrated timer-pulse unit (itu) programmable timing pattern controller (tpc) watchdog timer (wdt) a/d converter port b port a port 7 port 8 port 6 address bus port 9 refresh cotroller v ss v ss v cc v cc v cc p9 /t x d 0 p9 /t x d 1 p9 /r x d 2 p9 /r x d 3 4 p9 /sck /irq p9 /sck /irq 0 1 0 1 1 0 5 5 4 p7 /an 4 4 p7 /an 5 5 p7 /an 6 6 p7 /an 7 7 v ref pa /tp /tend /tclka 0 0 0 pa /tp /tend /tclkb 1 1 1 pb /tp /tioca 0 83 pb /tp /tiocb 1 93 pb /tp /dreq 6 14 0 pb /tp /dreq /adtrg 7 15 1 p8 /cs /irq 1 1 p8 /cs /irq 2 2 p8 /cs /irq 3 3 p8 /cs 0 4 reso dma controller (dmac) serial communication interface (sci) x2 channels 1 3 2
57 h8/3003 series md 0.10 2.70 -0.16 +0.20 0.1 3.05 max 0.8 0.3 1.6 0.17 +0.08 -0.05 0-5 0.65 29 28 1 56 57 20.0 84 85 112 0.30 + 0.10 - 0.13 o 23.2+ 0.3 - 23.2 0.3 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 a 0 av ss av cc pa /tp /tioca /tclkc 2 2 pb /tp /tioca 2 10 4 pb /tp /tiocb 3 11 4 pb /tp /tocxa 4 12 4 pb /tp /tocxb 5 13 4 pa /tp /tioca 4 41 pa /tp /tiocb 5 51 pa /tp /tioca 6 62 pa /tp /tiocb 7 72 p7 /an 0 0 p7 /an 1 1 p7 /an 2 2 p7 /an 3 3 0 pa /tp /tiocb /tclkd 3 3 0 p4 /d 0 0 p4 /d 1 1 p4 /d 2 2 p4 /d 3 3 p4 /d 4 4 p4 /d 5 5 p4 /d 6 6 p4 /d 7 7 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 v ss v ss v ss v ss lwr p8 /rfsh/irq 0 p6 /back 2 0 p6 /breq 1 p6 /wait 0 hwr rd as nmi res o xtal extal md md stby / 0 1 2 clock osc. h8/300h cpu data bus port 4 bus controller data bus (lower) data bus (upper) address bus interrupt controller ram 512 bytes 16-bit integrated timer-pulse unit (itu) programmable timing pattern controller (tpc) watchdog timer (wdt) a/d converter port b port a port 7 port 8 port 6 address bus port 9 refresh cotroller v ss v ss v cc v cc v cc p9 /t x d 0 p9 /t x d 1 p9 /r x d 2 p9 /r x d 3 4 p9 /sck /irq p9 /sck /irq 0 1 0 1 1 0 5 5 4 p7 /an 4 4 p7 /an 5 5 p7 /an 6 6 p7 /an 7 7 v ref pa /tp /tclka /tend 0 0 0 pa /tp /tclkb /tend 1 1 1 pb /tp /tioca 0 83 pb /tp /tiocb 1 93 pb /tp /dreq 6 14 0 pb /tp /dreq /adtrg 7 15 1 p8 /cs /irq 1 1 p8 /cs /irq 2 2 p8 /cs /irq 3 3 p8 /cs 0 4 reso dma controller (dmac) serial communication interface (sci) x2 channels p5 7 /a 23 p5 6 /a 22 p5 5 /a 21 p5 4 /a 20 pc 1 pc /dreq /cs 7 pc /irq 7 7 pc /irq 6 6 5 3 pc /tend /cs 6 4 3 pc /dreq /cs 5 3 2 pc /tend /cs 4 2 2 pc 0 port c 1 3 2 port 5
58 h8/3004 and h8/3005 series rd as wr p8 3 /irq 3 md m 0.50 21 25 1 40 41 12.0 60 14.0 0.2 61 80 0.20 0.05 0.10 14.0 0.2 0.10 0.17 0.05 0-5 o 0.00 min 0.20 max 1.20 max 1.00 0.50 0.10 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 pb / tioca 2 4 pb / tiocb 3 4 pb / tocxa 4 4 pb / tocxb 5 4 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 v ss v ss v ss nmi res ? xtal extal md md stby 0 1 2 clock osc. h8/300h cpu data bus port b port a port 7 port 8 port 9 v cc v cc v ref av ss av cc p9 /t x d 0 p9 /r x d 2 4 p9 /sck /irq 0 1 4 pa / tioca /tclkc 2 pa /tp /tioca /a 4 41 23 pa /tp /tiocb /a 5 51 22 pa /tp /tioca /a 6 62 21 pa /tp /tiocb /a 7 72 20 0 pa / tiocb /tclkd 3 0 pa / tclka 0 pa / tclkb 1 pb / tioca 0 3 pb / tiocb 1 3 pb 6 pb / adtrg 7 reso 0.10 2.70 -0.16 +0.20 0.10 3.05 max 0.80 0.30 1.60 m 0.17 +0.08 -0.05 0-5 0.65 21 20 1 40 41 14.0 60 61 80 0.30 0.10 0.12 o 17.2 0.3 17.2 0.3 address bus address bus data bus (upper) data bus (lower) p7 /an 0 0 p7 /an 1 1 p7 /an 2 2 p7 /an 3 3 p7 /an 4 4 p7 /an 5 5 p7 /an 6 6 p7 /an 7 7 p6 /wait 0 note: * 2 kbytes in the h8/3004, 4 kbytes in the h8/3005. interrupt controller watching timer 16-bit intrgrated timer unit (itu) ram* serial communication interface (sci) x 1 channel a/d converter a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 p8 2 /irq 2 p8 1 /irq 1 p8 0 /irq 0 port 6 wait-state controller bus controller
59 h8/3032 series md m 0.50 21 20 1 40 41 12.0 60 14.0 0.2 61 80 0.20 0.05 0.10 14.0 0.2 0.10 0.17 0.05 0-5 o 0.00 min 0.20 max 1.20 max 1.00 0.50 0.10 p2 0 /a 8 p2 1 /a 9 p2 2 /a 10 p2 3 /a 11 p2 4 /a 12 p2 5 /a 13 p2 6 /a 14 p2 7 /a 15 p5 0 /a 18 p5 1 /a 17 p5 2 /a 16 p5 3 /a 15 p1 1 /a 1 p1 2 /a 2 p1 3 /a 3 p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 p1 0 /a 0 pb /tp /tioca 2 10 4 pb /tp /tiocb 3 11 4 pb /tp /tocxa 4 12 4 pb /tp /tocxb 5 13 4 p3 7 /d 7 p3 6 /d 6 p3 5 /d 5 p3 4 /d 4 p3 3 /d 3 p3 2 /d 2 p3 1 /d 1 p3 0 /d 0 v ss v ss v ss p6 0 /wait nmi res ? xtal extal md md stby 0 1 2 clock osc. h8/300h cpu port 3 prom* (or masked rom) 16-bit integrated timer-pulse unit (itu) programmable timing pattern controller (tpc) port b port a port 7 port 8 port 6 port 1 port 9 v cc v cc av ss av cc v ref p9 /t x d 0 p9 /r x d 2 p9 /sck /irq 4 4 pa / tioca /tclkc 2 pa /tp /tioca 4 41 pa /tp /tiocb 5 51 pa /tp /tioca 6 62 pa /tp /tiocb 7 72 0 pa / tiocb /tclkd 3 0 pa / tclka 0 pa / tclkb 1 pb /tp /tioca 0 83 pb /tp /tiocb 1 93 pb /tp 6 14 pb /tp /adtrg 7 15 reso interrupt controller 0.10 2.70 -0.16 +0.20 0.12 3.05 max 0.80 0.30 1.60 m 0.17 +0.08 -0.05 0-5 0.65 21 20 1 40 41 14.0 60 61 80 0.30 0.10 0.12 o 17.2 0.3 17.2 0.3 port 2 port 5 data bus (upper) data bus (lower) p7 /an 0 0 p7 /an 1 1 p7 /an 2 2 p7 /an 3 3 p7 /an 4 4 p7 /an 5 5 p7 /an 6 6 p7 /an 7 7 p8 / irq 0 0 p8 / irq 1 1 p8 / irq 2 2 p8 / irq 3 3 p6 5 /wr p6 4 /rd p6 3 /as ram note: prom version is available only in the h8/3032 series. bus controller watchdog timer (wdt) serial connunication interface (sci) x 1 channel a/d converter
60 h8/3042 series md m 0.50 26 25 1 50 51 14.0 75 16.0 0.2 76 100 0.20 0.05 0.08 16.0 0.2 0.10 0.17 0.05 0-5 o 0.00 min 0.20 max 1.20 max 1.00 0.50 0.10 p2 0 /a 8 p2 1 /a 9 p2 2 /a 10 p2 3 /a 11 p2 4 /a 12 p2 5 /a 13 p2 6 /a 14 p2 7 /a 15 p5 0 /a 16 p5 1 /a 17 p5 2 /a 18 p5 3 /a 19 p1 1 /a 1 p1 2 /a 2 p1 3 /a 3 p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 p1 0 /a 0 pb /tp /tioca 2 10 4 pb /tp /tiocb 3 11 4 pb /tp /tocxa 4 12 4 pb /tp /tocxb 5 13 4 p4 0 /d 0 p4 1 /d 1 p4 2 /d 2 p4 3 /d 3 p4 4 /d 4 p4 5 /d 5 p4 6 /d 6 p4 7 /d 7 p3 7 /d 15 p3 6 /d 14 p3 5 /d 13 p3 4 /d 12 p3 3 /d 11 p3 2 /d 10 p3 1 /d 9 p3 0 /d 8 v ss v ss v ss v ss p6 2 /back p6 1 /breq p6 0 /wait nmi res ? xtal extal md md stby 0 1 2 clock osc. h8/300h cpu port 3 port 4 bus controller interrupt controller prom* (or masked rom) 16-bit integrated timer-pulse unit (itu) programmable timing pattern controller (tpc) watchdog timer (wdt) d/a converter port b port a port 7 port 8 port 6 port 1 port 9 refresh cotroller v ss v ss v cc v cc v cc av ss av cc v ref p9 /t x d 0 p9 /t x d 1 p9 /r x d 2 p9 /r x d 3 4 p9 /sck /irq p9 /sck /irq 0 1 0 1 1 0 5 5 4 pa /tp /tioca /tclkc 2 2 pa /tp /tioca /a 4 41 23 pa /tp /tiocb /a 5 51 22 pa /tp /tioca /a 6 62 21 pa /tp /tiocb /a 7 72 20 0 pa /tp /tiocb /tclkd 3 3 0 pa /tp /tend /tclka 0 0 0 pa /tp /tend /tclkb 1 1 1 pb /tp /tioca 0 83 pb /tp /tiocb 1 93 pb /tp /dreq 6 14 0 pb /tp /dreq /adtrg 7 15 1 reso dma controller (dmac) serial communication interface (sci) x2 channels 0.10 2.70 -0.16 +0.20 0.12 3.05 max 0.50 0.20 1.0 m 0.17 +0.08 -0.05 0-10 0.50 26 25 1 50 51 14 75 76 100 0.20 0.10 0.08 o 16.0 0.3 16.0 0.3 a/d converter port 2 port 5 address bus data bus (upper) data bus (lower) p7 /an 0 0 p7 /an 1 1 p7 /an 2 2 p7 /an 3 3 p7 /an 4 4 p7 /an 5 5 p7 /an /da 6 6 p7 /an /da 7 7 1 0 p8 /rfsh/irq 0 0 p8 /cs /irq 1 1 p8 /cs /irq 2 2 p8 /cs /irq 3 3 p8 /cs 0 4 1 3 2 p6 5 /hwr p6 4 /rd p6 3 /as p6 6 /lwr ram note: * h8/3042 only.
61 h8/3048 series md m 0.50 26 25 1 50 51 14.0 75 16.0 0.2 76 100 0.20 0.05 0.08 16.0 0.2 0.10 0.17 0.05 0-5 o 0.00 min 0.20 max 1.20 max 1.00 0.50 0.10 p2 0 /a 8 p2 1 /a 9 p2 2 /a 10 p2 3 /a 11 p2 4 /a 12 p2 5 /a 13 p2 6 /a 14 p2 7 /a 15 p5 0 /a 16 p5 1 /a 17 p5 2 /a 18 p5 3 /a 19 p1 1 /a 1 p1 2 /a 2 p1 3 /a 3 p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 p1 0 /a 0 pb /tp /tioca 2 10 4 pb /tp /tiocb 3 11 4 pb /tp /tocxa 4 12 4 pb /tp /tocxb 5 13 4 p4 0 /d 0 p4 1 /d 1 p4 2 /d 2 p4 3 /d 3 p4 4 /d 4 p4 5 /d 5 p4 6 /d 6 p4 7 /d 7 p3 7 /d 15 p3 6 /d 14 p3 5 /d 13 p3 4 /d 12 p3 3 /d 11 p3 2 /d 10 p3 1 /d 9 p3 0 /d 8 v ss v ss v ss v ss p6 2 /back p6 1 /breq p6 0 /wait nmi res ? xtal extal md md stby 0 1 2 clock pulse generator h8/300h cpu port 3 port 4 bus controller interrupt controller 16-bit integrated timer-pulse unit (itu) programmable timing pattern controller (tpc) watchdog timer (wdt) d/a converter port b port a port 7 port 8 port 6 port 1 port 9 refresh cotroller v ss v ss v cc v cc v cc av ss av cc v ref p9 /t x d 0 p9 /t x d 1 p9 /r x d 2 p9 /r x d 3 4 p9 /sck /irq p9 /sck /irq 0 1 0 1 1 0 5 5 4 pa /tp /tioca /tclkc 2 2 pa /tp /tioca /a / cs 4 41 23 pa /tp /tiocb /a / cs 5 51 22 pa /tp /tioca /a / cs 6 62 21 pa /tp /tiocb /a 7 72 20 0 pa /tp /tiocb /tclkd 3 3 0 pa /tp /tend /tclka 0 0 0 pa /tp /tend /tclkb 1 1 1 pb /tp /tioca 0 83 pb /tp /tiocb 1 93 pb /tp /dreq /cs 6 14 0 pb /tp /dreq /adtrg 7 15 1 vpp*/ reso dma controller (dmac) serial communication interface (sci) x2 channels 0.10 2.70 -0.16 +0.20 0.12 3.05 max 0.50 0.20 1.0 m 0.17 +0.08 -0.05 0-10 0.50 26 25 1 50 51 14 75 76 100 0.20 0.10 0.08 o 16.0 0.3 16.0 0.3 a/d converter port 2 port 5 address bus data bus (upper) data bus (lower) p7 /an 0 0 p7 /an 1 1 p7 /an 2 2 p7 /an 3 3 p7 /an 4 4 p7 /an 5 5 p7 /an /da 6 6 p7 /an /da 7 7 1 0 p8 /rfsh/irq 0 0 p8 /cs /irq 1 1 p8 /cs /irq 2 2 p8 /cs /irq 3 3 p8 /cs 0 4 1 3 2 p6 5 /hwr p6 4 /rd p6 3 /as p6 6 /lwr ram note: * vpp function is provided only for the flash memory version. 7 4 6 5 rom (masked rom, prom, or flash memory)
62 packages m 0.50 21 20 1 40 41 12.0 60 14.0 0.2 61 80 0.20 0.05 0.10 14.0 0.2 0.10 0.17 0.05 0-5 o 0.00 min 0.20 max 1.20 max 1.00 0.50 0.10 0.10 1.20 max m 0.17 0.05 0-5 0.65 26 25 1 50 51 14.0 75 76 100 0.20 0.05 0.08 o 16.0 0.2 16.0 0.2 m 0.50 26 25 1 50 51 14 75 16.0 0.3 76 100 0.20 0.10 0.08 16.0 0.3 0.15 2.70 -0.16 +0.20 0.20 3.05 max 1.20 0.20 2.40 m 0.17 0.05 0-10 0.65 31 30 1 50 51 20.0 80 81 80 0.30 0.10 0.13 o 18.8 0.4 24.8 0.4 0.10 0-10 o 0.10 2.70 -0.16 +0.20 0.10 3.05 max 0.8 0.30 1.6 m 0.17 0.5 0-5 0.65 29 28 1 56 57 20 84 85 112 0.30 0.10 0.13 o 23.2 0.3 m 0.65 21 20 1 40 41 14.0 60 17.2 0.3 61 80 0.20 0.05 0.12 17.2 0.3 23.2 0.3 0.10 0-5 o 14.0 2.70 -0.16 +0.20 0.12 3.05 max 0.50 0.20 1.0 0.17 -0.06 +0.08 fp-100a 1.00 0.50 0.10 0.00 min 0.20 max fp-100b tfp-100b fp-100b tfp-100b tfp-80c 2.70 -0.16 +0.20 0.10 3.05 max 0.17 -0.16 +0.20 0.8 0.30 1.60
63 ordering information the following tables show the available derivatives for each series within the h8/300h family. to build the actual part name append the desired clock rate to the part name's body. example: hd6413001f16 = h8/3001 in fp-80a package, 5v (10%), 16mhz. for details of the operating voltage range for rom-less derivatives, please refer to the selection guides on page 27.
64 h8/3001 body package suffix package/voltage/temp. available clock hd6413001 f tf vf vtf fl tfi vfi vtfi fp-80a/5v tfp-80c/5v fp-80a/low tfp-80c/low fp-80a/5v/-40 o c..85 0 c tfp-80c/5v/-40 o c..85 o c fp-80a/low/-40 o c..85 o c tfp-80c/low/-40 o c..85 o c 16,18 16,18 8,10,13 8,10,13 16,18 16,18 8,10,13 8,10,13 h8/3002 body package suffix package/voltage/temp. available clock hd6413002 f fp tf vf vfp vtf fl tfi vfi vtfl fj fq fp-100b/5v fp-100a*/5v tfp-100b/5v fp-100b/low fp-100a*/low tfp-100b/low fp-100b/5v/-40 o c..85 o c tfp-100b/5v/-40 o c..85 o c fp-100b/low/-40 o c..85 o c tfp-100b/low/-40 o c..85 o c fp-100b/5v/-40 o c..85 o c fp-100a*/5v/-40 o c..85 o c 10,12,16,17 16,17 10,12,16,17 8,10 8,10 8,10 10,12,16,17 10,12,16,17 8,10 8,10 10,12,16,17 16,17 h8/3003 body package suffix package/voltage/temp. available clock hd6413003 rf tf rvf tvf rfi tfi rvfi tvfi rfj tfj fp-112/5v fp-112/5v fp-112/low fp-112/low fp-112/5v/-40 o c..85 o c fp-112/5v/-40 o c..85 o c fp-112/low/-40 o c..85 o c fp-112/low/-40 o c..85 o c fp-112/5v/-40 o c..85 o c fp-112/5v/-40 o c..85 o c 10,12,16 10,12,16 8,10 8,10 10,12,16 10,12,16 8,10 8,10 10,12,16 10,12,16 note: for h8/3003 derivatives with a package suffix starting r, a crystal with double frequency is required, because of an internal divider by 2. h8/3004 body package suffix package/voltage/temp. available clock hd6413004 f te vf vte fl tei vfi vtei fj fp-80a/5v tfp-80c/5v fp-80a/low tfp-80c/low fp-80a/5v/-40 o c..85 o c tfp-80c/5v/-40 o c..85 o c fp-80a/low/-40 o c..85 o c tfp-80c/low/-40 o c..85 o c fp-80a/5v/-40 o c..85 o c 16,18 16,18 8,10 8,10 16,18 16,18 8,10 8,10 16,18 h8/3005 body package suffix package/voltage/temp. available clock hd6413005 f te vf vte fl tei vfi vtel fj fp-80a/5v tfp-80c/5v fp-80a/low tfp-80c/low fp-80a/5v/-40 o c..85 o c tfp-80c/5v/-40 o c..85 o c fp-80a/low/-40 o c..85 o c tfp-80c/low/-40 o c..85 o c fp-80a/5v/-40 o c..85 o c 16,18 16,18 8,10 8,10 16,18 16,18 8,10 8,10 16,18 * for availability of fp-100a please contact hitachi or an authorized distributor
65 for all of the parts with mask rom, ztat or flash the operating voltage range is 2.7..5.5v/8mhz, 3.0v..5.5v/10mhz, 3.15v..5.5v/13mhz and 4.5..5.5v otherwise. h8/3032 (ztat) body package suffix package/voltage/temp. available clock hd6473032 f tf vf vtf fl tfi vfi vtfi fj fp-80a/5v tfp-80c/5v fp-80a/low tfp-80c/low fp-80a/5v/-40 o c..85 0 c tfp-80c/5v/-40 o c..85 o c fp-80a/low/-40 o c..85 o c tfp-80c/low/-40 o c..85 o c fp-80a/5v/-40 o c..85 0 c 16,18 16,18 8,10 8,10 16,18 16,18 8,10 8,10 16,18 h8/3042 (ztat) body package suffix package/voltage/temp. available clock hd6473042s f fp tf vf vfp vtf fl tfi vfi vtfl fj fq fp-100b/5v fp-100a*/5v tfp-100b/5v fp-100b/low fp-100a*/low tfp-100b/low fp-100b/5v/-40 o c..85 o c tfp-100b/5v/-40 o c..85 o c fp-100b/low/-40 o c..85 o c tfp-100b/low/-40 o c..85 o c fp-100b/5v/-40 o c..85 o c fp-100a*/5v/-40 o c..85 o c 10,12,16,17 16,17 10,12,16,17 8,10 8,10 8,10 10,12,16,17 10,12,16,17 8,10 8,10 10,12,16,17 16,17 h8/3048 (ztat) body package suffix package/voltage/temp. available clock hd6473048s f tf vf vtf fi tfi vfi vtfi fj fp-100b/5v tfp-100b/5v fp-100b/low tfp-100b/low fp-100b/5v/-40 o c..85 o c tfp-100b/5v/-40 o c..85 o c fp-100b/low/-40 o c..85 o c tfp-100b/low/-40 o c..85 o c fp-100b/5v/-40 o c..85 o c 16,18 16,18 8,13 8,13 16,18 16,18 8,13 8,13 16,18 h8/3048 (f-ztat= flash memory) body package suffix package/voltage/temp. available clock hd64f3048 f tf vf vtf fi tfi vfi vtfi fj fp-100b/5v tfp-100b/5v fp-100b/low tfp-100b/low fp-100b/5v/-40 o c..85 o c tfp-100b/5v/-40 o c..85 o c fp-100b/low/-40 o c..85 o c tfp-100b/low/-40 o c..85 o c fp-100b/5v/-40 o c..85 o c 16 16 8 8 16 16 8 8 16
66 h8/3040 (pseudo rom-less version) this device is a mask rom h8/3040 with a blank rom, for which standard rom-less commercial criteria apply (e.g. minimum order quantity). the part names comply with the masked rom naming rule (please refer to next page). body vcc/clock suffix package suffix package/temperature hd6433040s a, p, t, v a, p, t, v a, p, t, v a, p, t, v a, p, t, v a, p a, p 00f 00fp 00tf 00fi 00tfi 00fj 00fq fp-100b fp-100a tfp-100b fp-100b/-40 o c..85 o c tfp-100b/-40 o c..85 o c fp-100b/-40 o c..85 o c fp-100a/-40 o c..85 o c vcc/clock suffix: a 16mhz/5v p 17mhz/5v t 10mhz/3.0..5.5v v 8mhz/2.7..5.5v example: hd6433040sa00fp is a pseudo rom-less h8/3040 in a fp-100a package, 16mhz, 5v and standard temperature (-20 o c..75 o c). * for availability of fp-100a please contact hitachi or an authorized distributor h8/3044 (pseudo rom-less version) this device is a mask rom h8/3044 with a blank rom, for which standard rom-less commercial criteria apply (e.g. minimum order quantity). the part names comply with the masked rom naming rule (please see below). it will be available in the first quarter 1997. body vcc/clock suffix package suffix package/temperature hd6433044s a, m, s, v a, m, s, v a, m, s, v a, m, s, v a, m 00f 00tf 00fi 00tfi 00fj fp-i00b tfp-i00b fp-100b/-40 o c..85 o c tfp-100b/-40 o c..85 o c fp-i00b/-40 o c..85 o c vcc/clock suffix: a m s v 16mhz/5v 18mhz/5v 13mhz/3.15..5.5v 8mhz/2.7..5.5v
67 naming rule for h8/300h mask rom parts hd643 + device body+ revision + code/speed + rom code + package device body revision rom code 4-digit code of desired h8/300h derivative, e.g. 3042 for h8/3042 s for mask revision or omitted, for new inquiries always use s 2-digit number assigned to mask after customer code submission code/speed a..e f..h k,l m p s t,u v,w 16mhz/5v 12mhz/5v 10mhz/5v 18mhz/5v 17mhz/5v 13mhz/3.15..5.5v i0mhz/3.0..5.5v 8mhz/2.7..5.5v when the rom code overflows (>99) the code/speed digit advances, e.g. from a99 to b00. package f fl fj fp fq tf tfi qfp qfp qfp qfp qfp tqfp tqfp 14mm x 14mm 14mm x 14mm 14mm x 14mm 14mm x 20mm 14mm x 20mm 14mm x 14mm 14mm x 14mm i-spec j-spec j-spec i-spec example: hd6433032smxxf is a mask rom h8/3032s (mask revision), with 18mhz/5v in fp-80a package (14mm x 14mm) in standard spec. xx will be determined after rom code submission.
68 microcontrollers for wide temperature range (wtr) all of hitachi's microcontrollers are available in several temperature ranges. the standard temperature range is -20 o c..75 o c and is not indicated in the package suffix. -40 o c..85 o c (i and j-spec) hitachi offers two specifications for -40 o c..85 o c. these are indicated in the package suffix by i and j. i-spec has a wider temperature range compared with standard spec, but has the same reliability. j-spec has improved reliability compared with standard spec. hitachi recommends to use j-spec for critical applications, particularly in industrial and automotive applications. -40 o c..105 o c (je-spec) je-spec has the same reliability as j-spec but extends the operating temperature range to 105 o c. this should - for example - be used in critical applications for automotive safety. -40 o c..125 o c (k-spec) k-spec further extends the temperature range to 125 o c and also improves reliability over je- spec. we recommend this for important safety features in the automotive market, where the product is installed e.g. near the engine. if you require je- or k-spec, please contact your hitachi sales office or authorized distributor.

▲Up To Search▲

Price & Availability of HD64F3048TFI16

	To Download HD64F3048TFI16 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .